Currently, power discrete semiconductor devices such as punch-through IGBTs (Insulated Gate Bipolar Transistors) may use inexpensive single-crystal silicon substrates manufactured by the FZ (Floating Zone) method, the MCZ (Magnetic field applied Czochralski) method, and the like to reduce cost.
A method for manufacturing a punch-through IGBT using an N-type single-crystal silicon substrate will be briefly described. First, an N+ diffusion layer (emitter layer), a P+ diffusion layer (base layer), a gate insulating film, a gate electrode, a metal interconnection (emitter electrode), and the like are formed on the top-surface side of a substrate. Then, the substrate is ground from the bottom-surface side thereof until the thickness of the substrate becomes, for example, 100 μm. Thereafter, an impurity is introduced into the substrate from the bottom surface of the substrate by ion implantation, and the impurity is activated by an electric oven, laser annealing, or the like, thus forming an N+ buffer layer and a P+ collector layer on the bottom-surface side of the substrate.
In conventional techniques, an N+ buffer layer is formed by implanting ions of, for example, phosphorus at an energy of approximately 500 keV to 8 MeV. Accordingly, the position at which the impurity concentration has a local maximum value is at a depth of approximately 5 μm at most from the bottom surface of the substrate.
Moreover, a P+ collector layer is formed by implanting ions of, for example, boron at a low energy of approximately 5 to 100 keV. Accordingly, the impurity (boron) is located at a depth of approximately 0.1 to 1.0 μm from the bottom surface of the substrate.
Generally, in a semiconductor device having an impurity distribution on the bottom-surface side of the substrate, it is desirable that the semiconductor substrate should be thinned to reduce a loss. The reduction of a loss achieved by thinning the substrate is a tradeoff against deteriorations in breakdown voltage characteristics and oscillations caused by a surge voltage increase during turn-off operation.
Patent literature 1 discloses a technique that forms an N+ buffer layer (field stop layer) by performing a plurality of cycles of proton irradiation. If disorder (near-amorphous state with a high crystal defect density) is formed in the substrate by proton irradiation, a leakage current may increase, or a loss caused by a carrier mobility reduction may increase. Accordingly, the invention of Patent literature 1 performs a plurality of cycles of proton irradiation. Specifically, a subsequent cycle of proton irradiation is targeted at the position of disorder remaining after the previous cycle of proton irradiation.
Patent literature 2 discloses a technique that forms an N+ buffer layer having a broad distribution by introducing oxygen into a semiconductor substrate and then performing proton irradiation.